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IBM Unveils World's First Sub-1 Nanometer Chip — 100 Billion Transistors on a Fingernail
IBM's new nanostack architecture pushes chip technology to the 0.7nm node, promising 50% more performance or 70% better efficiency
IBM has shattered the nanometer barrier. On June 25, the company unveiled the world's first sub-1 nanometer chip technology at the 0.7nm node — or 7 angstroms — marking a historic moment for an industry that has been racing against the physical limits of silicon.
The breakthrough comes via "nanostack," a new three-dimensional transistor architecture that vertically stacks and staggers nanosheet-based transistors. The result: nearly 100 billion transistors squeezed onto a chip the size of a fingernail, nearly double the density of IBM's own 2nm chip from 2021. IBM says the new design delivers up to 50 percent more performance or 70 percent greater energy efficiency compared to its 2nm node, and achieves 40 percent scaling in SRAM — a key metric for AI workloads.
"IBM's latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms," said Jay Gambetta, Director of IBM Research. "This industry-first innovation sets the foundation for the next era of computing." IBM projects that the nanostack architecture extends the semiconductor roadmap for at least another decade, with the technology experimentally validated through functional CMOS inverter operation — meaning it's not just a paper design, it physically works.
The announcement comes as the chip industry grapples with the slowdown of Moore's Law, where traditional transistor scaling has become exponentially harder. By moving into the third dimension with staggered nanosheet stacking, IBM's approach sidesteps the atomic-scale physics that have long been thought to cap progress somewhere around 1nm.
Sources: IBM Newsroom, Ars Technica
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